Using Partial Isolation Rings to Test Core-Based Designs

test challenge. Vendors of intellectual property cores usually give no information about a core’s internal logic (in other words, it is a black box). As a result, system designers cannot perform traditional test generation processes such as automatic test pattern generation (ATPG) and fault simulation. Instead, the core vendor specifies a set of test vectors that must be applied to the core to guarantee a certain fault coverage. The problem is how to apply the specified test vectors to the core and how to test the logic surrounding the core. One simple approach for testing embedded cores is to use multiplexing to make the core’s inputs and outputs accessible to the chip pins.1 But this approach does not help with testing the logic surrounding the core and thus results in degraded fault coverage. Another approach is to place an isolation ring around the core, as illustrated in Figure 1. An isolation ring is essentially a boundary scan that provides full controllability of the core’s inputs and full observability of the core’s outputs. It also provides full observability of the logic driving the core and full controllability of the logic driven by the core. The drawback of a full isolation ring is the large area and performance overhead it adds. It requires a boundary-scan element and associated routing for each input and output of the core and a multiplexer delay for every path to and from the core. As a result, a full isolation ring may not be an acceptable solution in many high-performance applications. Moreover, for a compact core with a large number of I/Os, adding a full isolation ring can more than double the area. We have developed a design-for-testability (DFT) method that reduces the area and performance overhead of using an isolation ring. This systematic procedure for designing a partial isolation ring provides the same fault coverage as a full isolation ring but avoids adding muxes on critical timing paths. Treating the core as a black box, the procedure assumes no information about the core other than the set of test vectors specified by the core supplier. The procedure uses ATPG techniques to analyze the user-defined logic (UDL) surrounding the core. This analysis identifies a maximal set of core inputs and outputs (including the critical timing paths) that need not be included in the partial isolation ring. If one core is driving another core, the procedure identifies a maximal set of isolation ring elements that can be removed from the interface between the cores.